Low-Latency LDPC Decoder for URLLC to be Presented at ESSERC 2025

Forward error correction (FEC) plays a critical role in modern wireless communication systems as it improves resilience against transmission errors. Ultra-reliable low-latency communication (URLLC), which is a key component of future 5G networks, demands FEC codes with short blocklengths, strong error-correction capabilities, and decoder implementations that offer both high throughput and minimal latency. While Polar codes with successive cancellation list (SCL) decoding typically outperform low-density parity-check (LDPC) codes using message-passing (MP) decoding in terms of block error rate (BLER), SCL decoders suffer from high latency, low area efficiency, and limited throughput.

To address these challenges, we present a new short-blocklength, multi-rate binary LDPC code that surpasses the performance of the LDPC code specified in the 5G standard at the same blocklengths. Designed specifically for low-latency applications, the proposed code supports fully parallel MP decoding. To demonstrate the effectiveness of our LDPC code, we developed a custom decoder ASIC that achieves an information throughput of 9 Gb/s with an energy efficiency of 62 pJ/b at a rate-1/2 code with a 128-bit blocklength. The fabricated chip delivers record-low decoding latency of only 14 ns, all within a compact silicon area of 0.44 mm² in GlobalFoundries 22nm FDX technology.

Our paper “A 14 ns-Latency 9 Gb/s 0.44 mm² 62 pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX,” co-authored by Darja Nonaca, Jérémy Guichemerre, Reinhard Wiesmayr, Engin Tunali, and Christoph Studer, will be presented at the 51st European Solid-State Electronics Research Conference (ESSERC 2025) in Munich.