First Silicon Implementation of a Jammer-Resilient Synchronization Method to Be Presented at ESSERC 2025

Jammer-resilient wireless communication systems are urgently needed. Spatial filtering based on multiple-input multiple-output (MIMO) processing is a promising approach to jammer mitigation. While there has been significant progress in the area of jammer-resilient data detection based on spatial filtering, there has been a lack of corresponding jammer-resilient time synchronization methods. Without successful time synchronization, data detection is impossible.

To remedy this situation, we present the first implementation of a jammer-resilient time synchronization method, JASS (short for Jammer-Aware SynchroniSation), in silicon. JASS mitigates smart jamming attacks on the synchronization sequence through adaptive spatial filtering. Our design supports a 16-antenna receiver and can mitigate attacks from jammers with up to two antennas and in which the jamming signal is up to 1000 times stronger than the synchronization signal. The fabricated 65nm ASIC has a core area of 2.87mm², consumes a power of 310mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).

Our paper "A Jammer-Resilient 2.87 mm² 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65nm" will be presented at the 51st European Solid-State Electronics Research Conference (ESSERC 2025) in Munich. It is co-authored by Flurin Arquint, who carried out this project as his Master's Thesis, and his supervisors Oscar Castañeda, Gian Marti, and Christoph Studer.