First Silicon Implementation for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

Wireless communication systems are at the mercy of interference, particularly from malicious agents. Fortunately, multi-antenna technology enables jammer-resilient data detectors based on spatial filtering. Last year, our group presented the first---and, until now, the only---jammer-resilient data detector in hardware. However, its error-rate performance is limited by the fact that it separates channel estimation from jammer mitigation and data detection.

To overcome this limitation, we present the first silicon implementation for the siMultaneous mitigAtion, Estimation and Detection (MAED) algorithm. MAED improves the error-rate performance as it iteratively refines the estimate of the legitimate communication channel together with those of the jammer channel and the transmitted data. We have implemented MAED for an 8-antenna receiver communicating with a single user equipment under the attack of a single-antenna jammer. Implemented in GlobalFoundries 22nm FDX technology, our MAED ASIC delivers a throughput of 100 Mb/s while consuming 223 mW in a core area of 0.32 mm², outperforming our previous jammer-resilient data detection ASIC in terms of per-user throughput and area efficiency, while preserving energy efficiency.

Our paper "A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection" will be presented at the 51st European Solid-State Electronics Research Conference (ESSERC 2025) in Munich. It is co-authored by Fabian Stuber and Jonas Elmiger, who carried out this project as a semester thesis, and their supervisors Oscar Castañeda, Gian Marti, and Christoph Studer.